The present invention relates to a method of manufacturing semiconductor devices having mask LDD (Lightly Doped Drain)-type high voltage MOS transistor with fewer manufacturing steps and the MOS transistor that is manufactured by the method. It particularly relates to a method of manufacturing semiconductor devices including high voltage MOS transistors whose maximum operating voltages are improved and the semiconductor devices that are manufactured by the method.
In order to drive a liquid crystal display device, for example, it is required that both low voltage MOS transistors which operate with a low power-supply voltage of, for example, 3.3V and high voltage MOS transistors which operate with a high power-supply voltage of, for example, 18V, are located on the same semiconductor substrate.
Among the above mentioned MOS transistors, a low voltage MOS transistor is, for example, formed in a well-known self-aligned LDD process as disclosed in reference 1. First, a gate insulation film is formed on a surface of an active area of a first conduction type in a surface of a semiconductor substrate, and a gate electrode is formed on the gate insulation film. Secondly, on both sides of the gate electrode, an LDD and lightly doped source layers are formed by implanting ions of impurities of a second conduction type at low concentration in a self-aligned process using gate electrode as a mask. Then, sidewall films are formed on sidewalls of the gate electrode, and the heavily doped source layer and heavily doped drain layer are then formed on the outside of the sidewall films by implanting ions of the impurities of the second conduction type at high concentration in a self-aligned process using the gate electrode and the sidewall films as a mask. In this method, the distance between the high concentration drain layer and the edge of the gate electrode is made equal to the width of the sidewall film.
On the other hand, it is necessary to make the gate insulation film of the high voltage MOS transistor thicker than that of the low voltage MOS transistor in order to improve the breakdown voltage between the gate and the source. Therefore, as disclosed in reference 1, a thick gate insulation film is formed first on the entire surface area of the semiconductor substrate by the thermal oxidation method, for example. The thick gate insulation film is then patterned by using a resist mask so that it is selectively removed in areas for forming low voltage MOS transistors. Then, the thin gate insulation film is formed again by a heat oxidation method, for example, in areas for forming low voltage MOS transistors.
For realizing a transistor with high breakdown voltage, it is also necessary to expand the distance between the gate electrode and the heavily doped drain layer to improve the breakdown voltage between the drain and the source. Therefore, for example, a structure of so-called “mask LDD” structure is utilized as disclosed in reference 1. In the “mask LDD” structure, heavily doped drain layer is formed with a certain distance apart from the gate electrode by implanting ions by using a resist mask. In this case, a low concentration layer whose conduction type is the same as the heavily doped drain layer is also formed between the edge of the gate electrode and the heavily doped drain layer, similar to the case of the LDD layer of the low voltage MOS transistor. Though this layer is named “high voltage area implanted by LDD” in reference 1, it is named a “grade area” in this specification.
However, there was a problem in that it was difficult to sufficiently increase the breakdown voltage (“breakdown voltage when operating” or “on-state breakdown voltage”) of this type of conventional MOS transistor. The problem was that when the drain voltage increases, the difference between the drain current and the source current increases, and the transistor destructs. This phenomenon of destruction depends on the concentrations of impurities of the grade area. However, the phenomenon occurs in the area of high gate voltages when the concentration is low, and in the area of low gate voltages when the concentration is high. Therefore, it is difficult to increase the breakdown voltage in both areas at the same time.
On the other hand, reference 2 discloses a semiconductor device comprising: a gate electrode formed on one conductive type semiconductor substrate through a gate insulation film; a high concentration reverse conductive type source region adjacent to one end of said gate electrode; a low concentration reverse conductive type drain region formed facing said source region through a channel region; a high concentration reverse conductive type drain region separated from the other end of said gate electrode and included in said low concentration reverse conductive type drain region; and a middle concentration reverse conductive type layer at a region spanning at least from the position having the predetermined space from said gate electrode to said high concentration reverse conductive type drain region, and formed so that high impurity concentration becomes lower at a region near the gate electrode than near said high concentration reverse conductive type drain region.
Reference 3 discloses the high breakdown voltage MOS transistor comprising a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a gate electrode formed on the gate insulation film; and an impurity diffusion layer formed by overlapping low, medium and high concentration impurity layers on the semiconductor substrate of at least one side of the gate electrode. Reference 3 also discloses the manufacturing method of the high breakdown voltage MOS transistor.    Reference 1: Official Gazette of Japanese Patent No. 3473902    Reference 2: Official Gazette of Japanese Laid-open Patent No. 2002-261276 Reference 3: Official Gazette of Japanese Laid-open Patent No. 8-172191
References 2 and 3 disclose an improvement in the breakdown voltage by adding the middle concentration layer in addition to the grade layer and the heavily doped drain layer. (In each reference, it is called the “middle concentration reverse conductive type layer,” and the “medium concentration impurity layers,” respectively.)
However, the manufacturing processes disclosed in the above references require forming the resist pattern to determine the position of the middle concentration layer. Therefore, a different photo-mask would be required in order to form the middle concentration layer, when the methods of forming the gate insulation film of two kinds of thicknesses disclosed in reference 1 are combined, for example, and the high voltage MOS transistor and low voltage MOS transistor are formed on the same semiconductor substrate. Also, it would be necessary to perform an additional process in order to form the resist pattern by using this different mask. Therefore, these process steps would increase the manufacturing cost.